Format |
Syntax: |
Operation: |
Operands: |
Architecture revision |
Opcode | ||||||||||||
1 |
stc0.d Rp[disp], CRs |
*(Rp + (ZE(disp12) << 2)) = CP#(CRd+1:CRd); |
p ∈ {0, 1, …, 15} s ∈ {0, 2, …, 14} s ∈ {0, 1, …, 15} disp ∈ {0, 4, …, 16380} |
Rev1+ |
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2 |
stc0.w Rp[disp], CRs |
*(Rp + (ZE(disp12) << 2)) = CP#(CRd); |
p ∈ {0, 1, …, 15} s ∈ {0, 2, …, 14} s ∈ {0, 1, …, 15} disp ∈ {0, 4, …, 16380} |
Rev1+ |
|
Stores the coprocessor 0 source register value to the location specified by the addressing mode.
Q: |
Not affected |
V: |
Not affected |
N: |
Not affected |
Z: |
Not affected |
C: |
Not affected |
stc0.d R2[0], CR0