Operations:

Format

Syntax:

Operation:

Operands:

Architecture revision

Opcode

1

stc0.d Rp[disp], CRs

*(Rp + (ZE(disp12) << 2)) = CP#(CRd+1:CRd);
p ∈ {0, 1, …, 15}
s ∈ {0, 2, …, 14}
s ∈ {0, 1, …, 15}
disp ∈ {0, 4, …, 16380}

Rev1+

111101111010

Rp

disp[11:8]

CRs[3:1]

0

disp[7:0]

12

4

4

3

1

8

2

stc0.w Rp[disp], CRs

*(Rp + (ZE(disp12) << 2)) = CP#(CRd);
p ∈ {0, 1, …, 15}
s ∈ {0, 2, …, 14}
s ∈ {0, 1, …, 15}
disp ∈ {0, 4, …, 16380}

Rev1+

111101011010

Rp

disp[11:8]

CRs

disp[7:0]

12

4

4

4

8

Description

Stores the coprocessor 0 source register value to the location specified by the addressing mode.

Status Flags:

Q:

Not affected

V:

Not affected

N:

Not affected

Z:

Not affected

C:

Not affected

Example:

stc0.d
R2[0], CR0